Half Adder in Digital Logic

Half adder is a combinational circuit that adds two one-bit numbers and generates sum and carry as an output

Half Adder in Digital Logic

4 steps that involved to construct any combinational circut:

  1. Decide how many number of input lines and output lines required for the circuit.
  2. Construct the truth table according to number of  input and output lines in which output as a function of input.
  3. Minimize the function using K-maps.
  4. Finally design the circuit by logical gates.

Step 1: Deciding number of input line and output lines for the hald-adder circuit:

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Step2: constructing Truth Table for Half-Adder:

A
B
Sum
Carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
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Step3:  Now, you can construct k-map or you can write directly final boolean equation using min-terms of above truth table.

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Step4:  design the circuit by logical gates.

    

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Therefore , to  design half Adder we need 1 XOR gate and 1 AND gate

Questions

1. How many minimum number of NAND gates are required to realise half Adder circut?

   ans:

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2. How many minimum NOR gates are required to realise half-adder circuit?

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